1. Field
This patent disclosure relates to phase-locked loops, and more particularly to a method and apparatus for phase-locked looping capable of stably operating with reduced adverse effects including jitters.
2. Discussion
In recent years, designers have sought to reduce the electrical power needs of electric equipment. Accordingly, the power applied to a PLL (phase-locked loop) circuit should be decreased as well.
FIG. 1 shows an exemplary circuit of a known VCO (voltage-controlled oscillator) 100 having a power source Vdd. In FIG. 1, the VCO 100 includes a ring oscillator 101, PMOS (P-channel metal oxide semiconductor) transistors P1-Pm, and NMOS (N-channel metal oxide semiconductor) transistors N1-Nm. The suffixes m of the PMOS and NMOS transistors Pm and Nm are an odd integers greater than 1. Further the VCO 100 includes a voltage-to-current conversion circuit 105, a first current mirror circuit 106, a second current mirror circuit 107, a third current mirror circuit 108, an NMOS (N-channel metal oxide semiconductor) transistor 109, and a constant current source 110.
The ring oscillator 101 includes inverter circuits IV1-IVm which form a delay circuit, wherein a suffix m is an odd integer greater than 1. The inverter circuits IV1-IVm are connected in a ring form. Each of the inverter circuits IV1-IVm of the ring oscillator 101 is composed of a pair of PMOS (P-channel metal oxide semiconductor) and NMOS (N-channel metal oxide semiconductor) transistors connected in series. The PMOS transistors P1-Pm are correspondingly connected to the inverter circuits IV1-IVm, respectively, and control a current flowing to a positive side power source terminal of the inverter circuits IV1-IVm from a direct current power source (not shown). The NMOS transistors N1-Nm are correspondingly connected to the inverter circuit IV1-IVm, respectively, and control a current flowing to a common ground from a negative side power source terminal of the inverter circuits IV1-IVm.
The voltage-to-current conversion circuit 105 includes an operational amplifier 102, an NMOS (N-channel metal oxide semiconductor) transistor 103, and a resistor 104. The operational amplifier 102 is configured to have a negative feedback, and outputs the input voltage VCOIN to a gate terminal of the NMOS transistor 103. Such operational amplifier 102 operates such that the voltage at the junction of the NMOS transistor 103 and the resistor 104 is substantially equal to the input voltage VCOIN. The current converted by the voltage-to-current conversion circuit 105 flows through the first, second, and third current mirror circuits 106, 107, and 108 and through the NMOS transistor 109.
The NMOS transistor 109 forms a current mirror circuit with each of the NMOS transistors N1-Nm and therefore, a current in accordance with the current output from the third current mirror circuit 108 flows through each of the NMOS transistors N1-Nm. The PMOS transistor 115 of the third current mirror circuit 108 forms a current mirror circuit with each of the PMOS transistors P1-Pm, and therefore each of the PMOS transistors P1-Pm supplies a current to a positive side power source terminal of corresponding one of the inverter circuits IV1-IVm in accordance with the current output from the second current mirror circuit 107.
In this way, a current flowing through each of the inverter circuits IV1-IVm can be controlled. That is, a delay time by each of the inverter circuits IV1-IVm can be controlled with using the input voltage VCOIN. Thereby, the VCO 100 can change the frequency of a signal SOUT output from the ring oscillator 101 with the input voltage VCOIN. In this type of PLL circuit, the oscillating frequency of the ring oscillator 101 is determined by the performances of the voltage-to-current conversion circuit 105 and the PMOS transistor 115. In particular, a minimum oscillating frequency of the ring oscillator 101 is determined by a resistance value of the resistor 104 provided to the voltage-to-current conversion circuit 105.
However, with the structure of the VCO 100, the frequency of the signal SOUT output from the ring oscillator 101 is not always linear, as seen in FIG. 2. More specifically, when the input voltage VCOIN is close to the power source voltage Vdd, the frequency of the signal SOUT linearly changes to an extent of a value obtained by subtracting a threshold voltage of the PMOS transistor 111 from the power source voltage Vdd.
That is, in a PLL circuit including the VCO 100 having a frequency characteristic shown in FIG. 2, the output frequency of the VCO 100 is linear relative to the input voltage VCOIN only in a narrow voltage range.
Therefore, it is needed to increase a gain of the VCO 100. However, if the gain of the VCO is increased, a variation of the output frequency per input voltage becomes greater and consequently the PLL circuit will have a greater jitter. As a result, the PLL decreases its performance.
In FIG. 2, a line A1 represents the frequency of the signal SOUT linearly increasing from a value greater than 0 as the input voltage VCOIN increases when a constant current source 110 is provided to the VCO 100, as shown in FIG. 1. A line A2 represents the frequency of the signal SOUT which linearly increases from 0, i.e., the ground level, when the constant current source 110 is not provided the VCO 100.
Generally, an area requiring a relatively high voltage remains in an input and output portion associated with an external component even in a process having a decreased source voltage. In such an area, a transistor having a relatively low performance but suitable for a high voltage use is applied. Under this circumstance, one method for preventing a PLL circuit from the degradation of its performance with an increasing jitter is to maintain a voltage of the whole PLL circuit at a high level by using a transistor for a high voltage use. In this method, however, a level shifter is needed between the PLL circuit and an internal logic circuit to be connected to the PLL circuit and therefore the PLL circuit will degrade in a duty cycle and a jitter.
This patent specification describes a novel phase-locked loop apparatus. In one example, a novel phase-locked loop apparatus includes a comparator, a filter, and a voltage-controlled oscillator. The comparator is configured to compare phases of a reference clock signal and an output signal of the apparatus and to output a voltage in accordance with a difference in phase as a comparison result. The filter is configured to integrate the voltage output from the comparator. The voltage-controlled oscillator is configured to control a frequency of an output signal in accordance with the voltage output from the filter. This voltage-controlled oscillator includes a ring oscillator, a plurality of first transistors, a plurality of second transistors, a voltage-to-current converter, a first current mirror circuit, a second current mirror circuit, and a third current mirror circuit. The ring oscillator is configured to include a delay circuit including a plurality of inverters connected in a ring form. The plurality of first transistors correspond to the plurality of inverters of the ring oscillator on a one-to-one basis and are configured to control a current supplied by a first power source voltage to a positive side power source terminal of each of the plurality of inverters. The plurality of second transistors correspond to the plurality of inverters of the ring oscillator on a one-to-one basis and are configured to control a current output from a negative side power source terminal of each of the plurality of inverters. The voltage-to-current converter is configured to convert the voltage output from the filter into a current. The first current mirror circuit is configured to output a current in accordance with the current output from the voltage-to-current converter. The second current mirror circuit is configured to output a current in accordance with the current output from the first current mirror circuit to a control signal input terminal of each of the plurality of first transistors. The third current mirror circuit is configured to output a current in accordance with the current output from the second current mirror circuit to a control signal input terminal of each of the plurality of second transistors. In this apparatus, the voltage-to-current converter, the first and second current mirror circuits operate with a second power source voltage greater than the first power source voltage, and the ring oscillator and the third current mirror circuit operate with the first power source voltage.
The voltage-to-current converter may include a transistor and resistor series circuit and an operational amplifier. The transistor and resistor series circuit includes a transistor and a resistor in series and configured to convert an input voltage into a current. The operational amplifier has a non-inverse terminal receiving the voltage output from the filter and an inverse terminal connected to an output terminal of the transistor of the transistor and resistor series circuit to form a negative feedback circuit. The operational amplifier is configured to control an operation of the transistor of the transistor and resistor series circuit.
The voltage-to-current converter may include a constant current source configured to supply a predetermined constant current to the first current mirror circuit.
The third current mirror circuit may include a transistor with which each of the plurality of first transistors forms a current mirror circuit.
The voltage-to-current converter may include a third transistor configured to form a current mirror circuit with each of the plurality of second transistors and to receive a current output from the third current mirror circuit.
This patent specification further describes another novel phase-locked loop apparatus which in one example, includes a comparator, a filter, and a voltage-controlled oscillator. The comparator is configured to compare phases of a reference clock signal and an output signal of the apparatus and to output a voltage in accordance with a difference in phase as a comparison result. The filter is configured to integrate the voltage output from the comparator. The voltage-controlled oscillator is configured to control a frequency of an output signal in accordance with the voltage output from the filter, the voltage-controlled oscillator comprising a ring oscillator, a VCO, and first, second and third current mirror circuits. The ring oscillator is configured to include a delay circuit including a plurality of differential amplifiers connected in a ring form. Each of the plurality of differential amplifier includes a first transistor for controlling a current supplied to a corresponding one of the plurality of differential amplifiers by a first power source voltage and a second transistor for controlling a current output from a corresponding one of the plurality of differential amplifiers. The voltage-to-current converter (VCO) is configured to convert the voltage output from the filter into a current. The first current mirror circuit is configured to output a current in accordance with the current output from the voltage-to-current converter. The second current mirror circuit is configured to output a current in accordance with the current output from the first current mirror circuit to a control signal input terminal of the first transistor included in each of the plurality of differential amplifiers. The third current mirror circuit is configured to output a current in accordance with the current output from the second current mirror circuit to a control signal input terminal of the second transistor included in each of the plurality of differential amplifiers. In this apparatus, the voltage-to-current converter, the first and second current mirror circuits operate with a second power source voltage greater than the first power source voltage, and the ring oscillator and the third current mirror circuit operate with the first power source voltage.
This patent specification further describes a novel method of phase-locked looping. In one example, the novel method including the steps of providing, comparing, generating, integrating, converting, first mirroring, second mirroring, third mirroring, first applying, and second applying. The providing step provides a ring oscillator including a plurality of inverters connected in a ring form. The comparing step compares phases of a reference clock signal and an output signal of the apparatus. The generating step generates a voltage in accordance with a difference in phase as a comparison result. The integrating step integrates the voltage output from the generating step. The converting step converts the voltage output from the integrating step into a current. The first mirroring step mirrors the current converted in the converting step to output a current in accordance with the current output from the converting step. The second mirroring step mirrors the current output in the first mirroring step to output a first current in accordance with the current output in the first mirroring step. The third mirroring step mirrors the current output in the second mirroring step to output a second current in accordance with the current output from the second mirroring step. The first applying step applies the first current output in the second mirroring step to a plurality of first transistors corresponding to the plurality of invertors of the ring oscillator on a one-to-one basis to control a current supplied by a first power source voltage to a positive side power source terminal of each of the plurality of invertors. The second applying step applies the second current output in the third mirroring step to a plurality of second transistors corresponding to the plurality of invertors of the ring oscillator on a one-to-one basis to control a current output from a negative side power source terminal of each of the plurality of invertors. In this apparatus, the converting step, the first and second mirroring steps operate with a second power source voltage greater than the first power source voltage, and the ring oscillator and the third mirroring step operate with the first power source voltage.
This patent specification further describes another novel method of phase-locked looping which, in one example, includes the step of providing, comparing, generating, integrating, converting, first mirroring, second mirroring, third mirroring, first applying, and second applying. The providing step provides a ring oscillator including a plurality of differential amplifiers connected in a ring form. Each of the plurality of differential amplifiers includes first and second transistors. The comparing step compares phases of a reference clock signal and an output signal of the apparatus. The generating step generates a voltage in accordance with a difference in phase as a comparison result. The integrating step integrates the voltage output from the generating step. The converting step converts the voltage output from the integrating step into a current. The first mirroring step mirrors the current converted in the converting step to output a current in accordance with the current output from the converting step. The second mirroring step mirrors the current output in the first mirroring step to output a first current in accordance with the current output in the first mirroring step. The third mirroring step mirrors the current output in the second mirroring step to output a second current in accordance with the current output from the second mirroring step. The first applying step applies the first current output in the second mirroring step to the first transistor included in each of the plurality of differential amplifiers of the ring oscillator to control a current supplied by a first power source voltage to each of the plurality of differential amplifiers. The second applying step applies the second current output in the third mirroring step to the second transistor included in each of the plurality of differential amplifiers of the ring oscillator to control a current output from a negative side power source terminal of each of the plurality of differential amplifiers. In this apparatus, the converting step, the first and second mirroring steps operate with a second power source voltage greater than the first power source voltage, and the ring oscillator and the third mirroring step operate with the first power source voltage.